Some test strategies for 3D integrated circuits

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dc.contributor.authorKaibartta, Tanusree
dc.date.accessioned2022-10-31T05:19:40Z
dc.date.available2022-10-31T05:19:40Z
dc.date.issued2022-09
dc.identifier.urihttp://hdl.handle.net/123456789/2540
dc.language.isoenen_US
dc.publisherIndian Institute of Technology (Indian School of Mines) Dhanbaden_US
dc.subjectCoreen_US
dc.subjectTAMen_US
dc.subjectSOCen_US
dc.subject3D ICen_US
dc.subjectwrapperen_US
dc.subjectSICen_US
dc.subjectPSOen_US
dc.subjectPh.Den_US
dc.subjectCSEen_US
dc.subjectPH2245en_US
dc.titleSome test strategies for 3D integrated circuitsen_US
dc.typeThesisen_US
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