Designing hardware architectures for real-time image processing

Simple item page
dc.contributor.authorMukherjee, Debasish
dc.date.accessioned2020-10-15T11:23:30Z
dc.date.available2020-10-15T11:23:30Z
dc.date.issued2020-07
dc.identifier.urihttp://hdl.handle.net/123456789/1783
dc.language.isoenen_US
dc.publisherIndian Institute of Technology (Indian School of Mines), Dhanbaden_US
dc.subjectReal-time image processingen_US
dc.subjectSingle Window Separable Convolution (SWSC)en_US
dc.subjectMulti Window Separable Convolution (MWSC)en_US
dc.subjectFPGA platformsen_US
dc.subjectDiscrete Cosine Transform (DCT)en_US
dc.subjectGaussian filteren_US
dc.subjectPh.Den_US
dc.subjectCSEen_US
dc.subjectPH1589en_US
dc.titleDesigning hardware architectures for real-time image processingen_US
dc.typeThesisen_US
Files
Original bundle
Now showing 1 - 2 of 2
Thumbnail Image
Name:
Abstract.pdf
Size:
6.77 KB
Format:
Adobe Portable Document Format
Description:
Download
Thumbnail Image
Name:
PH1589.pdf
Size:
6.49 MB
Format:
Adobe Portable Document Format
Description:
Download
License bundle
Now showing 1 - 1 of 1
No Thumbnail Available
Name:
license.txt
Size:
1.71 KB
Format:
Item-specific license agreed upon to submission
Description:
Download
Collections
S Mukhopadhyay