FPGA implementation of hardware efficient adaptive filter for low computational complexity
| dc.contributor.author | Abbas, Syed Jafar | |
| dc.date.accessioned | 2024-10-08T10:29:24Z | |
| dc.date.available | 2024-10-08T10:29:24Z | |
| dc.date.issued | 2024-05 | |
| dc.identifier.uri | http://hdl.handle.net/123456789/3860 | |
| dc.language.iso | en | en_US |
| dc.publisher | Indian Institute of Technology (Indian School of Mines) Dhanbad | en_US |
| dc.subject | Real life applications | en_US |
| dc.subject | Mean square (LMS) algorithm | en_US |
| dc.subject | Pipelined version | en_US |
| dc.subject | DIST | en_US |
| dc.subject | DS1433 | en_US |
| dc.subject | ECE | en_US |
| dc.title | FPGA implementation of hardware efficient adaptive filter for low computational complexity | en_US |
| dc.type | Thesis | en_US |
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