Design of low power digital circuits in deep submicron CMOS technologies

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Thesis.pdf (4.29 MB)
Date
2014-03
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Indian Institute of Technology (Indian School of Mines), Dhanbad
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Description
Keywords
Dynamic power dissipation, Leakage power dissipation, Deep submicron, Nanoscale device, Super cutoff CMOS (SCCMOS) technique, ECE, Ph.D
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http://hdl.handle.net/123456789/854
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Sajal K. Paul