Design of low power digital circuits in deep submicron CMOS technologies

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dc.contributor.authorKumar, Manish
dc.date.accessioned2017-11-21T11:44:39Z
dc.date.available2017-11-21T11:44:39Z
dc.date.issued2014-03
dc.identifier.urihttp://hdl.handle.net/123456789/854
dc.language.isoenen_US
dc.publisherIndian Institute of Technology (Indian School of Mines), Dhanbaden_US
dc.subjectDynamic power dissipationen_US
dc.subjectLeakage power dissipationen_US
dc.subjectDeep submicronen_US
dc.subjectNanoscale deviceen_US
dc.subjectSuper cutoff CMOS (SCCMOS) techniqueen_US
dc.subjectECEen_US
dc.subjectPh.Den_US
dc.titleDesign of low power digital circuits in deep submicron CMOS technologiesen_US
dc.typeThesisen_US
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